(1. ) Field of the Invention
The present invention relates to a semiconductor memory device with a redundant function, and more particularly, to a semiconductor memory device provided with a redundant memory cell (cell array) wherein the redundant function can be released from the outside if necessary.
(2) Description of the Related Art
The larger the scale of a semiconductor memory device, the higher the probability of the generation of a faulty memory cell, and thus redundant (spare) memory cells are provided. If a faulty memory cell is found during a test, the faulty memory cell is replaced with the redundant memory cell, and increases the production rate.
The replacement of the faulty memory cell with the redundant memory cell is usually performed at a memory device production step. Namely, in the final step of testing the wafer, a faulty memory cell in each chip is detected by a tester, and when a faulty memory cell or cells is detected, the possibility of the replacement thereof is examined (for example, the number of the faulty word lines is not larger than the number of redundant (spare) word lines available). If replacement is possible, the faulty memory cells are replaced with redundant memory cells and the process advances to detect a faulty memory cell in the next chip.
After the faulty memory cells are replaced with the redundant memory cells, the faulty memory cells are not distinguished from the outside, since the replaced memory cell is no different from the normal memory cell (cell array). Namely, when using the memory device, it is impossible to determine by an external examination whether or not the memory cells have been replaced by redundant memory cells. This is most inconvenient when attempting to discover the cause of a fault, as it is important to know whether or not a redundant memory cell is being used, and if a redundant memory cell is being used, to know the location (or address) of the faulty memory cell. Therefore, although the extraction of the output of the ROM (read only memory) for storing the redundant (faulty) memory cell address or the like has been attempted, nevertheless it cannot be determined whether any one of word lines or bit lines in a block is faulty when a sequential plurality of lines has been replaced as a block. In addition, even if the faulty word line or bit line address is determined by reading the outputs of the redundant address ROM, it cannot be determined whether a memory cell on the word line or bit line is faulty.
In addition, the faulty state, e.g., malfunction by voltage fluctuation, malfunction caused by read/write speed, increase of faulty area, cannot be determined.
The art regarding a semiconductor memory device with a redundant memory cell wherein the address of the replaced faulty memory cells can be known, is disclosed in Japanese Unexamined Patent Publications (Kokai) No. 59-217300 (filed Dec. 7, 1984) and No. 60-151899 (filed August 9, 1985).